VLSI Projects in Bangalore for ECE

A 32-bit RISC processor with a 5-stage pipeline (IF, ID, EX, MEM, WB) is designed in Verilog and implemented on a Xilinx Artix-7 FPGA. The instruction set supports 32 instructions including arithmetic, logical, load/store, and branch operations. Hazard detection and forwarding units resolve data and control hazards. The processor executes a bubble-sort benchmark of 100 integers in 1,240 clock cycles at 50 MHz. Synthesis reports show a resource utilisation of 1,847 LUTs and a maximum frequency of 78 MHz. A UART interface allows program loading from a PC terminal.

An AES-128 encryption core implementing the SubBytes, ShiftRows, MixColumns, and AddRoundKey transformations is designed in Verilog using a fully unrolled 10-round architecture. The core processes one 128-bit block per clock cycle after a 10-cycle pipeline fill, achieving a throughput of 6.4 Gbps at 50 MHz on a Spartan-6 FPGA. A self-checking testbench verifies all 128 NIST test vectors. Synthesis results show 4,200 LUTs and a maximum frequency of 85 MHz. The project demonstrates cryptographic hardware design, pipelining, and FPGA resource optimisation.

A parameterised UART transmitter and receiver are designed in Verilog supporting baud rates from 9600 to 921600 bps with configurable data bits (7/8), parity (none/even/odd), and stop bits (1/2). A 16-byte FIFO buffer is included on both TX and RX paths. A comprehensive testbench applies 10,000 random transactions and checks for framing errors, parity errors, and FIFO overflow conditions. The design is synthesised on a Cyclone IV FPGA and verified by looping TX to RX at 115200 bps. Resource utilisation is 312 LEs and 32 memory bits.

An 8-bit ALU supporting 16 operations (ADD, SUB, AND, OR, XOR, NOT, SHL, SHR, MUL, DIV, CMP, and four rotate operations) is designed in Verilog with clock-gating cells inserted at the module level to disable unused functional units. Power analysis in Xilinx Vivado shows a 28% reduction in dynamic power compared to the baseline design without clock gating. A testbench with 500 directed test cases and 1,000 random vectors achieves 100% functional coverage. The project demonstrates low-power RTL design techniques applicable to battery-operated SoC designs.

A full-duplex SPI master controller is designed in VHDL supporting all four SPI modes (CPOL/CPHA combinations), configurable clock dividers (2× to 256×), and 8-bit to 32-bit transfer widths. An APB slave interface allows a host processor to configure registers and initiate transfers. A loopback testbench connects MOSI to MISO and verifies 2,000 random transactions across all modes. The design is implemented on an Artix-7 FPGA and demonstrated communicating with an external SPI flash memory at 25 MHz. Synthesis shows 187 LUTs and a maximum frequency of 120 MHz.

A hardware accelerator for Sobel edge detection is designed in Verilog and implemented on a Xilinx Artix-7 FPGA. The design reads 8-bit grayscale pixel data from BRAM, applies 3×3 Sobel kernels in the X and Y directions using a line-buffer architecture, computes gradient magnitude, and writes the result back to BRAM. Processing a 640×480 image takes 307,200 clock cycles at 100 MHz, achieving a throughput of 32 frames per second. Resource utilisation is 2,100 LUTs and 6 BRAM blocks. The project demonstrates streaming datapath design and hardware image processing.

A finite-state machine controlling a 4-way traffic intersection is designed in Verilog with 12 states representing all green, yellow, and all-red phases for each direction. Pedestrian crossing requests are handled as asynchronous inputs that extend the current green phase by 5 seconds. The FSM is implemented on a Basys3 FPGA board with seven-segment displays showing countdown timers and LEDs representing signal states. A testbench applies all pedestrian request combinations and verifies that no conflicting green phases occur simultaneously. The project demonstrates FSM design, timing constraints, and FPGA I/O interfacing.

A simplified DDR3 memory controller is designed in Verilog implementing the initialisation sequence, mode register writes, activate, read, write, and precharge commands per JEDEC JESD79-3F. The controller interfaces with a Micron DDR3 simulation model and is verified with a testbench that performs 10,000 random read/write transactions at 800 MHz data rate. Timing parameters (tRCD, tRP, tRAS, tCL) are parameterised for easy retargeting. The project demonstrates advanced VLSI design skills including high-speed memory interface protocols, timing closure, and simulation-based verification methodology.

A Viterbi decoder for a rate-1/2, constraint-length-7 convolutional code is designed in VHDL using the add-compare-select (ACS) butterfly structure with a 64-state trellis. The decoder processes 1 bit per clock cycle and outputs decoded bits after a 32-symbol trace-back depth. A testbench generates 100,000 random information bits, encodes them, adds AWGN at various Eb/N0 levels, and measures bit error rate. At Eb/N0 = 5 dB, the decoder achieves a BER of 1.2×10⁻⁵, matching theoretical performance. Synthesis on Cyclone IV shows 3,800 LEs and a maximum frequency of 65 MHz.